1. Field of the Invention
The present invention relates to data processing systems employing virtual memory partitioned into pages and having a channel which communicates with an input-output (I/O) device adapter. More particularly, the present invention relates to apparatus for formulating channel error status information and placing this information on an I/O event stack accessible by the central processing unit (CPU).
2. Description of the Prior Art
In a data processing system having a channel which communicates with an I/O device adapter a variety of errors may occur. These errors may be simple parity errors occurring during a transfer of information on a bus or they may be errors relating to the particular data field formats and operational sequences defined for the channel interface with the I/O adapter. In most systems, the detection of an error at the channel interface causes the system to stop, at or near the point of error. This strategy allows trouble-shooting personnel to identify the failing device and the type of error. The obvious disadvantage is that an entire system may be brought to a halt as a result of an error occurring in one I/O adapter.
One known prior art arrangement for dealing with channel interface errors is shown in U.S. Pat. No. 3,810,120, issued to Huettner, et al. This patent shows an apparatus for detecting a failure or error in any one of several peripheral devices connected to a common input/output bus. Upon detecting the failure, the failed peripheral device is disabled automatically. A second known prior art arrangement appears in U.S. Pat. No. 4,016,548 issued to Law, et al. which shows a communications multiplexer module which can detect certain kinds of I/O device errors. It appears, however, that neither of these arrangements provides identification of the failing I/O device to the CPU or assembles the error or failure status information for later fetching by the CPU and possible error recovery action.